With sustaining reduction in weight and thickness of electronic equipment, the technique of high density packaging of a semiconductor device is steadily progressing in keeping pace with miniaturization and integration of the semiconductor device itself. Heretofore, in packaging a semiconductor element, a wire bonding connection that uses gold wiring traces, for example, and a flipchip connection that uses a solder ball, are used for interconnecting a wiring board of a package and the semiconductor element.
In the wire bonding connection, packaging may be performed to advantage at a low cost in case there are a smaller number of pads of the semiconductor element. It is however necessary to reduce the wire diameter as the pitch of pads of the semiconductor element becomes narrower. As a result, there has been a problem of lowering in the yield in the assembly process due to wire breakages, or the like.
The flipchip connection, as compared to the wire bonding connection, may provide for high-speed transmission between the semiconductor element and the wiring board. However, the connection strength of the solder ball is lowered as the number of pads of the semiconductor element is increased and as the pitch of the pads becomes narrower. As a result, cracking or the like defects occur frequently at the connection sites.
Recently, a technique of enclosing a semiconductor element in a wiring board inclusive of a support substrate, a so-called semiconductor element enclosing technique, has been proposed in, for example, Patent Documents 1 to 3. This technique represents a high density packaging technique that has implemented higher integration and higher functions of semiconductor devices. In addition, the technique has a number of merits including inter alia a thinner package thickness, low costs, accommodation to higher frequencies, low-stress plating connection and an improved electro-migration characteristic etc.
Patent Document 1, for example, discloses a technique in which an electronic component burying board is a laminated board composed of a resin film and a metal foil. A component burying recess is formed in the resin film, and an electronic component is buried and secured in the recess. The resulting assembly is pressed under heating and subjected to processing with a heated roll for lamination to form a conductor wiring.
Patent Document 2 discloses a structure in which an electronic circuit is enclosed in a board of an insulating resin in which there is buried an electronic component such as a semiconductor chip. Bumps are formed so as to be connected to the electronic circuit, and is connected to a first interconnection.
Patent Document 3 discloses a structure of a semiconductor element accommodating package configured to suppress heat-induced flexure or warping. The structure includes a board on which to set the semiconductor element, a frame of, for example, an epoxy resin, and a plurality of lead terminals on an inner surface of the frame. The lead terminals are each provided with a widened portion whose width progressively increases towards an outer part of the frame.    Patent Document 1:    JP Patent Kokai Publication No. JP2002-141636A    Patent Document 2:    JP Patent Kokai Publication No. JP2007-134569A    Patent Document 3:    JP Patent Kokai Publication No. JP2004-200243A